New materials could boost energy efficiency of microelectronics

Massachusetts Institute of Technology (MIT) researchers have unveiled a new materials and chip-fabrication approach that could dramatically improve the energy efficiency of future microelectronic devices. The breakthrough tackles one of computing’s chronic problems: the enormous amount of energy wasted as data moves back and forth between logic and memory components on a chip. In modern processors, these units are typically placed side-by-side, forcing electrical signals to travel long distances. That journey wastes power as heat and slows performance, especially in data-heavy tasks like artificial intelligence and machine learning.
The MIT team developed a low-temperature method that allows new electronic components to be built directly on top of already-fabricated circuits, enabling true vertical stacking. This is possible thanks to a new channel material, amorphous indium oxide, which can form high-quality, ultra-thin transistor layers at around 150 °C — a temperature low enough to avoid damaging the silicon circuitry beneath. By stacking components in this way, the distance that signals travel shrinks dramatically, cutting energy losses and boosting overall efficiency.
The researchers also demonstrated memory transistors using a second material, ferroelectric hafnium–zirconium oxide, creating compact devices only about 20 nanometres wide. These memory elements can switch states in roughly 10 nanoseconds while consuming far less power than comparable technologies. Combining logic and memory so closely in a vertical structure opens the door to “compute-in-memory” architectures, where data can be processed and stored in the same location rather than constantly shuttling across the chip.
As global demand for computing continues to soar, especially from AI, cloud platforms and edge devices, energy use has become a critical bottleneck. Data centres already consume staggering amounts of electricity and without new materials and architectures, the energy cost of computation will become increasingly unsustainable. According to lead researcher Yanjie Shao, reducing this footprint requires more than incremental improvements; it demands new fabrication platforms that rethink how electronic components are arranged and how they interact.
The team believes this stacked fabrication method provides such a platform. Beyond its immediate performance benefits, it offers a way to experiment with new material combinations, new geometries and entirely new device concepts that conventional silicon processes cannot accommodate. The researchers now aim to refine the technique further and integrate more complex layers, pushing towards chip architectures that are faster, smaller and dramatically more energy-efficient.
If successful, this innovation could reshape the future of microelectronics, offering a pathway to sustainable high-performance computing at a time when the world’s technological appetite — and energy consumption — continues to grow.